Due to high demands of portable devices, power consumption has become a major concern in chip design, especially in embedded memories, in particular static random access memory (SRAM). Memory can contribute significantly to the power consumption of the chip or chips of the device.
For reducing the power consumption of a memory device, it has been proposed to reduce the power supply voltage of memory devices. A reduction of the power supply voltage can reduce the power required for charging electrically conductive lines in the memory device, in particular wordlines and bitlines, to the power supply voltage.
However, in SRAM devices operated at a relatively low power supply voltage, a reduced writability of memory cells of the SRAM device can be an issue, since a voltage applied to a transistor in a memory cell may be insufficient for overcoming the threshold voltage of the transistor. Technology scaling may increase this problem, since a reduction of critical dimensions of circuit elements of the memory devices may lead to an increase of process variation and, hence, to a broader distribution of threshold voltages of transistors in the memory device. The reduced writability of memory cells can be a serious threat to the functionality of memory devices and thus to the yield of the manufacturing of memory devices.
To address the problem of a reduced writability of memory devices, various write assist methods have been proposed. Such methods include a reduction of the power supply voltage for columns of memory cells, a negative bitline approach, wherein bitlines of the memory device are charged to a voltage smaller than ground voltage during writing processes, a raising of the ground voltage for columns of memory cells during writing processes, and boosted wordline schemes, wherein it is attempted to overdrive access transistors of memory cells. However, the existing approaches can lead to an increase of the power consumption of the memory device, or may require a relatively large chip area for required circuitry, and can be unsuitable for low speed, low power applications such as medical applications.
U.S. Pat. No. 6,934,213 discloses an example of a method and a circuit for reducing power consumption during write operations in a RAM. In a RAM comprising of a plurality of memory cells, the bit lines that are coupled to each memory cell in the RAM and used to read and write data into the cell are coupled through charge share control circuitry to a charge sharing line. During write operations, the bit line that will receive a zero value is coupled to the charge share line before data is written to the cell. The charge share line equalizes the charge on the selected bit line and the charge share line and reduces the voltage differential that must be swung to write data into the cell.
In the method of U.S. Pat. No. 6,934,213, bitlines (which can be true bitlines and complementary bitlines) are never pulled down to ground voltage, since, due to the charge sharing with the charge sharing line that is performed instead of grounding the bitlines, the bitlines are never discharged completely. This can reduce the voltage between gate and source of field effect transistors in the memory cells compared to memory devices wherein the bitlines are completely discharged. Under low writability conditions of a memory cell, wherein the memory cell has a relatively low write voltage, this can have the consequence that the memory cell is not writeable. For example, if the charge share line attains a voltage of 300 mV and the write voltage of the memory cell is 150 mV, the memory cell cannot be written, even if the raising of the ground voltage of the memory cell that is provided by the charge share line helps to improve the writability of the memory cell to a certain extent. If deep submicron technologies are employed for the manufacturing of a memory device, the spread of write voltages of memory cells in a memory device can be relatively high, which increases the likelihood of write failure occurring. These issues can adversely affect the functionality of a memory device according to U.S. Pat. No. 6,934,213, in particular if it is operated at a low power supply voltage.
It is an object of the present subject matter to provide a memory device and a method of operation thereof that help to overcome the above-mentioned problems.